US 12,412,632 B2
Managing compensation for charge coupling and lateral migration in memory devices
Mustafa N. Kaynak, San Diego, CA (US); Patrick R. Khayat, San Diego, CA (US); and Sivagnanam Parthasarathy, Carlsbad, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 14, 2024, as Appl. No. 18/744,146.
Application 18/744,146 is a continuation of application No. 17/860,690, filed on Jul. 8, 2022, granted, now 12,046,298.
Claims priority of provisional application 63/348,293, filed on Jun. 2, 2022.
Prior Publication US 2024/0331778 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/26 (2006.01); G06F 3/06 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/26 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G11C 16/3459 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a set of aggressor memory cells of the memory device that are adjacent to a specified memory cell of the memory device;
generating a list of programming level states for the set of aggressor memory cells, wherein each entry in the list specifies, for each aggressor memory cell in the set, a respective number of bits used to reflect the programming level of the aggressor memory cell, and wherein a total number of bits specified by each entry is associated with a corresponding maximum read window budget (RWB) increase;
identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to a target RWB increase, the entry comprising a lowest number of bits;
adjusting, based on the maximum RWB increase, a memory access parameter value; and
performing, using the adjusted memory access parameter value, a memory access operation with respect to the specified memory cell.