| CPC G11C 16/0483 (2013.01) [G11C 5/063 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 16 Claims |
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1. A flash memory, which is an AND-type flash memory and comprises a memory cell array, wherein the memory cell array comprises a plurality of memory cells, and the plurality of memory cells are connected in parallel between a source line and a bit line, wherein the flash memory comprises:
a plurality of diffusion regions formed in a substrate in a column direction;
a plurality of gates formed between the opposite diffusion regions;
a first selection control line connected to each gate of a bit line side selection transistor in a row direction;
a second selection control line connected to each gate of a source line side selection transistor in the row direction; and
a plurality of word lines connected to gates of the memory cells in the row direction,
wherein each of the bit line side selection transistor, the source line side selection transistor, and the plurality of memory cells has a channel area in the row direction, and
the diffusion regions comprise:
a first isolation region electrically isolating a diffusion region of the bit line side selection transistor from a diffusion region of the memory cell adjacent to the bit line side selection transistor; and
a second isolation region electrically isolating a diffusion region of the source line side selection transistor from a diffusion region of the memory cell adjacent to the source line side selection transistor, wherein the first isolation region and the second isolation region have a different conductivity type from other diffusion regions.
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