| CPC G11C 11/4096 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4091 (2013.01)] | 15 Claims |
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1. A memory device comprising:
a capacitor;
a first transistor that has a first end coupled to the capacitor;
a first inverter circuit that is coupled between a first node and a second node and includes a p-type second transistor and an n-type third transistor coupled in series at a third node;
a second inverter circuit that is coupled between the first node and the second node and includes a p-type fourth transistor and an n-type fifth transistor coupled in series at a fourth node, the fifth transistor having a gate coupled to a second end of the first transistor;
a sixth transistor coupled between the gate of the fifth transistor and the third node;
a seventh transistor coupled between a gate of the third transistor and the fourth node;
an eighth transistor coupled between the gate of the third transistor and the third node; and
a ninth transistor coupled between the gate of the fifth transistor and the fourth node, wherein
a state in which a first voltage is applied to the first node and a second voltage lower than the first voltage is applied to the second node is formed at a first time, a third voltage between the second voltage and the first voltage is applied to the first node at a second time after the first time, a fourth voltage between the second voltage and the first voltage is applied to the second node at a third time after the second time, the second voltage is applied to the second node at a fourth time after the third time, and the first voltage is applied to the first node at a fifth time after the fourth time.
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