US 12,412,620 B2
Second word line combined with y-mux signal in high voltage memory program
Yoshitaka Yamauchi, Hsinchu (TW); Meng-Sheng Chang, Chu-bei (TW); Hiroki Noguchi, Hsinchu (TW); and Perng-Fei Yuh, Walnut Creek, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,559.
Application 18/361,559 is a continuation of application No. 17/331,340, filed on May 26, 2021, granted, now 11,763,875.
Prior Publication US 2023/0377629 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4087 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory cells arranged over a plurality of rows and a plurality of columns;
wherein each of the memory cells comprises:
a first metal-oxide-semiconductor (MOS) transistor coupled to a corresponding one of a plurality of first word lines, wherein the plurality of first word lines are arranged along the plurality of rows;
a second MOS transistor coupled to the first MOS transistor and a corresponding one of a plurality of second word lines, wherein the plurality of second word lines are arranged along the plurality of columns;
a memory element; and
a third MOS transistor;
wherein the third MOS transistor, the memory element, the second MOS transistor, and the first MOS transistor are connected in series, and wherein the first MOS transistor and the second MOS transistor are one of n-type MOS (NMOS) transistors or p-type MOS (PMOS) transistors, and the third MOS transistor is another one of NMOS transistor or PMOS transistor different from the first and second MOS transistors.