US 12,412,618 B2
Buffer chip, and semiconductor package including buffer chip and memory chip
Choung Ki Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 14, 2023, as Appl. No. 18/509,188.
Claims priority of application No. 10-2023-0008378 (KR), filed on Jan. 19, 2023; application No. 10-2023-0008379 (KR), filed on Jan. 19, 2023; application No. 10-2023-0008380 (KR), filed on Jan. 19, 2023; application No. 10-2023-0008381 (KR), filed on Jan. 19, 2023; and application No. 10-2023-0100176 (KR), filed on Aug. 1, 2023.
Prior Publication US 2024/0249765 A1, Jul. 25, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 11/4076 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01)
CPC G11C 11/4076 (2013.01) [H01L 24/48 (2013.01); H01L 25/18 (2013.01); H10B 80/00 (2023.02); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A buffer chip comprising:
a control signal transmission path transmitting, to a memory chip, control signals transmitted from a memory controller;
a data transmission path including a variable delay circuit having a delay value adjusted by a delay code and transmitting, to the memory controller, data transmitted from the memory chip;
a ring oscillator generating a ring oscillator clock;
a counter circuit configured to count the number of toggles of the ring oscillator clock while an external clock toggles a reference number of times;
a reference value storage circuit configured to store a counting value of the counter circuit as a reference value in response to a reference setting signal;
a current value storage circuit configured to store the counting value of the counter circuit as a current value in response to a comparison signal; and
a code generation circuit configured to generate the delay code by comparing the reference value with the current value.