| CPC G11C 11/4023 (2013.01) [G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01)] | 4 Claims |
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1. An energy-efficient memory for cryogenic computing, comprising a plurality of memory banks, wherein each of the plurality of memory banks comprises a cryogenic semi-static, dual-port, boost-free gain cell (CSDB-GC) macro module, a universal address decoder, and a different address decoder, wherein
the CSDB-GC macro module comprises a plurality of columns of local blocks, wherein all local blocks in a same column share a same global bitline n (GBLn), a same global bitline p (GBLp), and two sense amplifiers (SAs) connected to the GBLn and the GBLp, each of the plurality of columns of local blocks comprises a plurality of CSDB-GC memory cells, all CSDB-GC memory cells of a same local block are connected to a local bitline n (LBLn) and a local bitline p (LBLp), different local blocks have different LBLns and LBLps, each LBLn is connected to the GBLn through a corresponding bitline switch SWn, each LBLp is connected to the GBLp through a corresponding bitline switch SWp, and the SWn and the SWp are controlled to be closed to select a corresponding local block in a column, wherein an LBLn and an LBLp of the selected local block are connected to the GBLn and the GBLp respectively;
a wordline n (WLn) of each of the plurality of CSDB-GC memory cells is directly connected to the universal address decoder, a wordline p (WLp) is selectively connected to the universal address decoder or the different address decoder based on control logic, the different address decoder is activated only when two different data addresses are received, the universal address decoder is activated to implement a single-port read operation of the CSDB-GC memory cell, and the different address decoder is activated to implement a dual-port read operation of the CSDB-GC memory cell; and
each of the plurality of CSDB-GC memory cells comprises dual ports provided by a first n-type access transistor and a first p-type access transistor, and an internal data regeneration loop constituted by a second n-type transistor and a second p-type transistor,
a bitline n (BLn) connected to the first n-type access transistor and a bitline p (BLp) connected to the first p-type access transistor are respectively connected to the LBLn and the LBLp, the WLn is connected to the first n-type access transistor, and the WLp is connected to the first p-type access transistor;
during a write operation, data 0 or 1 is written into a node Vn through the first n-type access transistor, and the data 1 or 0 is written into a node Vp through the first p-type access transistor;
when the first n-type access transistor transmits a weak signal ‘1’ to the node Vn or the first p-type access transistor transmits a weak signal ‘0’ to the node Vp, the weak signal ‘1’ or the weak signal ‘0’ enables the second n-type transistor and the second p-type transistor to be turned on, the node Vn is connected to a VDD through the second p-type transistor, and the node Vp is connected to a GND through the second n-type transistor, wherein the weak signal ‘1’ represents a voltage lower than the VDD and the weak signal ‘0’ represents a voltage higher than the GND; and
during a read operation, the first n-type access transistor and/or the first p-type access transistor are/is turned on to read data stored in the node Vn and/or the node Vp, and when voltages of the node Vn and the node Vp experience a disturbance, the second n-type transistor and the second p-type transistor are turned on, allowing the node Vn and the node Vp to be connected to the VDD and the GND respectively.
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