| CPC G11C 11/1673 (2013.01) [G11C 7/08 (2013.01); G11C 11/1675 (2013.01)] | 8 Claims |
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1. A semiconductor device comprising:
a bit line;
a first memory cell that is connected to the bit line and includes a first storage element of a variable resistance type;
a second memory cell that is connected to the bit line, includes a second storage element having same electrical characteristics as the first storage element, and is used as a One Time Programmable (OTP) cell;
a clamp element configured to apply a fixed potential to the bit line at a time of a readout operation;
a reference current source configured to generate a reference current;
a sense amplifier configured to apply the fixed potential to the first memory cell or the second memory cell at the time of the readout operation to detect, by using the reference current, a magnitude of a cell current flowing through the bit line; and
an offset current source that is activated at a time of the readout operation for the second memory cell, and is configured to generate, at a time of being activated, an offset current to be subtracted from the cell current,
wherein, at the time of the readout operation for the second memory cell, the sense amplifier detects a magnitude relationship between the reference current and a readout current obtained by subtracting the offset current from the cell current.
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