| CPC G09G 3/3241 (2013.01) [G09G 3/3233 (2013.01); H10K 50/86 (2023.02); H10K 59/1216 (2023.02); H10K 59/131 (2023.02); H10K 59/40 (2023.02); H10K 59/65 (2023.02); H10K 59/8791 (2023.02); H10K 77/111 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0297 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/021 (2013.01); G09G 2330/04 (2013.01); G09G 2360/14 (2013.01); H10K 2102/311 (2023.02)] | 11 Claims |

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1. A display device comprising:
a first display region configured to display an image;
a second display region configured to display an image, the second display region having a lower pixel density than the first display region;
a first metal layer;
a second metal layer located upper than the first metal layer; and
a third metal layer located upper than the first metal layer and the second metal layer,
wherein occupancy of the third metal layer in the second display region is lower than occupancy of the third metal layer in the first display region,
wherein the first display region includes a plurality of first pixel units and each of the plurality of first pixel units includes:
a light-emitting element including an upper electrode region, a lower electrode region, and a light-emitting layer located between the upper electrode region and the lower electrode region; and
a driving transistor configured to control light emission of the light-emitting element,
wherein the first metal layer, the second metal layer, and the third metal layer are located lower than the lower electrode region,
wherein, in each of the plurality of first pixel units, the first metal layer includes a first electrode region configured to control an amount of electric current in a channel of the driving transistor,
wherein, in each of the plurality of first pixel units, the second metal layer includes a second electrode region and a third electrode region configured to supply electric current to the channel of the driving transistor, and
wherein, in each of the plurality of first pixel units, the third metal layer includes:
a main region configured to be supplied with a power supply potential and form a capacitor included in a first capacitive element with the second metal layer, the first capacitive element being configured to store a voltage to control the driving transistor; and
an island region separated from the main region and surrounded by the main region with a gap, the island region being interconnected with the lower electrode region by a via region.
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