US 12,412,332 B2
Native sampler feedback technology
Daniel Johnston, Portland, OR (US); Yoav Harel, Carmichael, CA (US); and Subhajit Dasgupta, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,244.
Prior Publication US 2023/0094067 A1, Mar. 30, 2023
Int. Cl. G06T 15/04 (2011.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01)
CPC G06T 15/04 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A computing system comprising:
a host processor; and
a graphics processor coupled to the host processor, wherein the graphics processor includes sampler logic coupled to one or more substrates, the sampler logic to:
determine mip region dimensions of a feedback map based on a description of the feedback map, identify accessed texels in a texture based on a view of a resource that is paired with the feedback map, and record the accessed texels in the feedback map based on the mip region dimensions;
wherein the graphics processor further includes a native copy operation to transfer mip region information between the feedback map and an application resource, wherein the native copy operation is to operate via one or more of:
bypassing a padded portion of the feedback map, or
bypassing, by the mip region information, a color compression surface.