US 12,412,241 B2
Demosaicing circuit for demosaicing quad bayer raw image data
Sarvesh Swami, San Jose, CA (US); David R. Pope, Campbell, CA (US); Sheng Lin, San Jose, CA (US); and Amnon D. Silverstein, Palo Alto, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 1, 2024, as Appl. No. 18/429,536.
Application 18/429,536 is a continuation of application No. 17/578,127, filed on Jan. 18, 2022, granted, now 11,972,538.
Prior Publication US 2024/0169481 A1, May 23, 2024
Int. Cl. G06K 9/00 (2022.01); G06T 3/4007 (2024.01); G06T 3/4015 (2024.01); G06T 5/20 (2006.01)
CPC G06T 3/4015 (2013.01) [G06T 3/4007 (2013.01); G06T 5/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for demosaicing image data, comprising:
a logic circuit configured to receive image data from one or more image sensors and to determine whether the received image data is in a first image format or a second image format;
a first demosaicing circuit coupled to the logic circuit and a shared memory and configured to perform first demosaicing operations on the received image data to generate first full-color image data as an output responsive to the received image data being in the first image format; and
a second demosaicing circuit coupled to the logic circuit and the shared memory and configured to perform second demosaicing operations on the received image data to generate second full-color image data as the output responsive to the received image data being in the second image format, wherein the shared memory comprises a first number of buffers allocated to the first demosaicing circuit and a second number of buffers allocated to the second demosaicing circuit.