| CPC G06N 3/063 (2013.01) | 18 Claims |

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1. A z-first reference neural processing circuitry (NPU) for mapping Winograd Convolution supporting both direct convolution (DConv) mode and Winograd convolution (WgConv) mode, the NPU comprising:
memory banks configured to store input feature maps (IFMs) in a z-first data storage layout, each of the memory banks being configured to store the IFMs in one of the DConv mode or the WgConv mode;
a reconfigurable IFM distributor circuitry configured to receive the IFMs from the memory banks;
a parallel reconfigurable Winograd forward transform circuitry configured to receive the IFMs from the reconfigurable IFM distributor and to transform the IFMs in a Winograd domain to transformed IFMs in the WgConv mode;
multiply and accumulate (MAC) circuitries configured to perform dot product operations on one of IFMs in the DConv mode and the transformed IFMs in the WgConv mode to obtain intermediate output feature maps (OFMs); and
a reconfigurable OFM adder and Winograd inverse transform circuitry configured to generate one of an OFM from the intermediate OFMs in the DConv mode and OFMs from the intermediate OFMs in the WgConv mode,
wherein each of the memory banks are further configured to store a batch of IFMs from the IFMs in the DConv mode and store channels of each of coordinates of each of the IFMs in the WgConv mode as IFM blocks.
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