US 12,412,074 B2
Method for in-memory convolutional computation and corresponding integrated circuit
Antonino Conte, Tremestieri Etneo (IT); and Francesco La Rosa, Rousset (FR)
Assigned to STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR); and STMICROELECTRONICS S.R.L., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT); and STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Aug. 3, 2021, as Appl. No. 17/393,075.
Claims priority of application No. 2008327 (FR), filed on Aug. 6, 2020.
Prior Publication US 2022/0044099 A1, Feb. 10, 2022
Int. Cl. G06N 3/045 (2023.01); G06N 3/065 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01)
CPC G06N 3/045 (2023.01) [G06N 3/065 (2023.01); G11C 13/0004 (2013.01); H10B 63/32 (2023.02); G11C 13/004 (2013.01); G11C 13/0069 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for convolutional computation (CNVL) of input values with weight factors, the method comprising:
converting the input values to voltage signals and successively applying the voltage signals on selected bit lines in an array of non-volatile memory points over respective time slots, each non-volatile memory point comprising a phase-change resistive memory cell coupled to a bit line and having a resistive state corresponding to a weight factor, and a bipolar selection transistor coupled in series with the phase-change resistive memory cell and having a base terminal coupled with a word line, wherein the respective voltage signals bias the respective phase-change memory cells, and wherein the bipolar selection transistors are provided with a β-gain less than 1;
integrating over successive time slots read currents resulting from the voltage signals biasing the respective phase-change resistive memory cells and flowing through selected word lines; and
converting integrated read currents to output values.