US 12,412,021 B2
Layout design support apparatus, layout design support method, and manufacturing method of semiconductor device
Tadashi Kiyuna, Kanagawa (JP)
Assigned to ABLIC Inc., Nagano (JP)
Filed by ABLIC Inc., Tokyo (JP)
Filed on Oct. 16, 2022, as Appl. No. 17/966,878.
Claims priority of application No. 2021-193734 (JP), filed on Nov. 30, 2021.
Prior Publication US 2023/0169254 A1, Jun. 1, 2023
Int. Cl. G06F 30/398 (2020.01); G06F 119/06 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 2119/06 (2020.01)] 11 Claims
OG exemplary drawing
 
1. A layout design support apparatus for an integrated circuit in which a plurality of circuit elements having different breakdown voltages coexist, the layout design support apparatus comprising:
a storage device storing circuit connection data of the integrated circuit combining circuit components which comprise a first external terminal, a second external terminal, and the circuit elements to which element type information and breakdown voltage information are to be added;
an input device receiving first potential information to be added to the first external terminal; and
a control device which
determines, in the circuit element connected to the first external terminal to which the first potential information is added, whether to short-circuit one terminal connected to the first external terminal and another terminal based on a determination criterion according to the element type information and the breakdown voltage information,
adds the first potential information to the circuit components on a path from the first external terminal to the one terminal of the circuit element to identify a first equipotential region according to determining not to short-circuit the one terminal and the another terminal of the circuit element, and
repeatedly performs determination for the circuit element connected to the another terminal and identifies the first equipotential region according to determining to short-circuit the one terminal and the another terminal of the circuit element,
wherein the control device identifies a second equipotential region when the input device receives second potential information to be added to the second external terminal.