US 12,411,996 B2
Hardware-based implementation of secure hash algorithms
Manoj Kumar, Yorktown Heights, NY (US); Silvia Melitta Mueller, St. Ingbert (DE); Debapriya Chatterjee, Austin, TX (US); Niels Fricke, Herrenberg (DE); Kattamuri Ekanadham, Mohegan Lake, NY (US); Maarten J. Boersma, Holzgerlingen (DE); and Martijn Diede Berkers, Boeblingen (DE)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 10, 2022, as Appl. No. 17/884,704.
Prior Publication US 2024/0061961 A1, Feb. 22, 2024
Int. Cl. G06F 21/72 (2013.01); H04L 9/06 (2006.01)
CPC G06F 21/72 (2013.01) [H04L 9/0643 (2013.01); H04L 2209/12 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A processor, comprising:
an instruction fetch unit that fetches instructions to be processed in the processor;
a register file including a plurality of registers for storing source operands and destination operands; and
an execution unit for executing a hash instruction obtained from the instructions, wherein the execution unit includes a hash circuit including at least:
a state register,
a state update circuit coupled to the state register,
a control circuit, and
a single instruction multiple data (SIMD) adder, wherein the SIMD adder is a dedicated component of the hash circuit,
wherein the execution unit, based on the hash instruction, is configured to perform:
receiving from the register file and buffering within the state register a current state of a message being hashed;
performing, in the state update circuit, a state update function on contents of the state register, wherein:
the state update function comprises a Secure Hash Algorthim 2 (SHA2) block hash function;
performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register; and
following completion of all of the plurality of iterative rounds of processing, adding, by the SIMD adder, contents of the state register to a current state of the message being hashed and storing a resulting sum to the register file as an updated state of the message.