US 12,411,770 B2
Hybrid parallel programming of single-level cell memory
Umberto Siciliani, Rubano (IT); Violante Moschiano, Avezzano (IT); and Walter Di Francesco, Avezzano (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 29, 2024, as Appl. No. 18/649,582.
Application 18/649,582 is a continuation of application No. 17/585,165, filed on Jan. 26, 2022, granted, now 12,001,336.
Claims priority of provisional application 63/224,274, filed on Jul. 21, 2021.
Prior Publication US 2024/0281378 A1, Aug. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0842 (2016.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G06F 12/0842 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); G11C 16/3459 (2013.01); G06F 2212/1024 (2013.01)] 20 Claims
OG exemplary drawing
 
18. A memory device comprising:
a page buffer comprising a cache register and at least one data register;
a memory array, configured as single-level cell (SLC) memory, comprising a set of sub-blocks coupled with the page buffer; and
control logic operatively coupled with the page buffer, the control logic to perform operations comprising:
receive, from a host system, a program page cache command comprising a first page of SLC data and a first page address, wherein the host system has stored the first page of SLC data in the cache register;
moving the first page of SLC data from the cache register to the at least one data register;
causing a subsequent page of the SLC data received from the host system with a second page address to be stored in the cache register; and
concurrently causing:
the first page of SLC data to be programmed from the at least one data register to the first page address at a first sub-block of the set of sub-blocks; and
the subsequent page of the SLC data to be programmed from the cache register to the second page address of a second sub-block of the set of sub-blocks;
wherein at least some of the operations for programming the first page and the subsequent page of the SLC data to the set of sub-blocks are to be performed in parallel.