US 12,411,768 B2
Cache memory device and method for implementing cache scheduling using same
Do Hun Kim, Yongin-si (KR); Keebum Shin, Seongnam-si (KR); and Kwangsun Lee, Yongin-si (KR)
Assigned to XCENA Inc., Seongnam-si (KR)
Filed by XCENA Inc., Seongnam-si (KR)
Filed on Apr. 12, 2024, as Appl. No. 18/634,662.
Application 18/634,662 is a continuation of application No. 18/508,840, filed on Nov. 14, 2023, granted, now 11,994,991.
Claims priority of application No. 10-2023-0051365 (KR), filed on Apr. 19, 2023.
Prior Publication US 2024/0354252 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/0817 (2016.01); G06F 12/0877 (2016.01)
CPC G06F 12/0828 (2013.01) [G06F 12/0877 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A cache memory device comprising:
a request reception unit configured to receive input transactions;
a traffic monitoring module configured to monitor traffic of the input transactions;
N cache schedulers, wherein N is an integer greater than or equal to 2;
a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein the input transactions are transferred via an input transaction region set in each cache scheduler; and
an access execution unit configured to perform cache memory accesses to the input transactions scheduled by the N cache schedulers,
wherein the region setting module is further configured to set the N input transaction regions based on traffic of first input transactions during a first predetermined period before a time point of performing the setting of the N input transaction regions.