US 12,411,767 B2
Coherent memory system
Krishna T. Malladi, San Jose, CA (US); Andrew Z Chang, Los Altos, CA (US); and Ehsan Najafabadi, Duluth, GA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 9, 2021, as Appl. No. 17/372,309.
Claims priority of provisional application 63/185,842, filed on May 7, 2021.
Prior Publication US 2022/0358042 A1, Nov. 10, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0817 (2016.01)
CPC G06F 12/0828 (2013.01) [G06F 2212/621 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system, comprising:
a first memory device, the first memory device comprising:
a cache coherent controller connected to a processing circuit over a cache coherent interface;
a volatile memory controller;
a volatile memory;
a nonvolatile memory controller; and
a nonvolatile memory,
wherein the first memory device is configured:
to receive a quality of service requirement; and
to selectively enable a first feature in response to the quality of service requirement;
wherein the cache coherent interface is configured to transport a first data packet between the processing circuit and the volatile memory via the cache coherent controller, and is further configured to transport a second data packet between the processing circuit and the nonvolatile memory via the cache coherent controller,
wherein the cache coherent controller is configured to translate at least the first data packet that is based on an interface of the volatile memory to a data packet that is based on the cache coherent interface,
wherein the first feature comprises a memory management unit cache in the first memory device; and
the first memory device is configured to:
allocate a portion of the volatile memory as the memory management unit cache, and
perform a physical address lookup, in the memory management unit cache, of a physical address, based on a virtual address.