US 12,411,761 B1
Fully cache coherent virtual partitions in multitenant configurations in a multiprocessor system
Adarsha Rao S J, Karnataka (IN); Sanjay R. Deshpande, San Jose, CA (US); Raghuram L, Karnataka (IN); Anirudh B K, Karnataka (IN); Harsh Kumar, San Jose, CA (US); and Kun Fang, San Jose, CA (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Mar. 7, 2024, as Appl. No. 18/598,997.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 9/52 (2006.01); G06F 12/02 (2006.01); G06F 12/0831 (2016.01); G06F 12/0895 (2016.01)
CPC G06F 12/0246 (2013.01) [G06F 9/3004 (2013.01); G06F 9/3885 (2013.01); G06F 9/5077 (2013.01); G06F 9/52 (2013.01); G06F 12/0831 (2013.01); G06F 12/0895 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for processing memory operations in a multiprocessor system, the method comprising:
determining that a first memory operation generated by a first partition of an auxiliary processor is directed to a first memory address that is owned by a second partition of the auxiliary processor;
associating the first memory address with the first partition;
transferring an ownership of the first memory address from the second partition to the first partition; and
returning data stored at the first memory address to the first partition.