US 12,411,696 B2
Programmable hardware accelerator controller
Paolo Sergio Zambotti, Milan (IT); Thomas Boesch, Rovio (CH); Giuseppe Desoli, San Fermo Della Battaglia (IT); Wolfgang Johann Betz, Agrate Brianza (IT); and David Siorpaes, Cortina d'Ampezzo (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT); and STMicroelectronics International N.V., Geneva (CH)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT); and STMicroelectronics International N.V., Geneva (CH)
Filed on Feb. 28, 2023, as Appl. No. 18/176,323.
Claims priority of provisional application 63/477,738, filed on Dec. 29, 2022.
Prior Publication US 2024/0220278 A1, Jul. 4, 2024
Int. Cl. G06F 9/445 (2018.01); G06F 9/38 (2018.01); G06F 9/448 (2018.01); G06F 9/50 (2006.01)
CPC G06F 9/44505 (2013.01) [G06F 9/3836 (2013.01); G06F 9/4498 (2018.02); G06F 9/5038 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A device, comprising:
a hardware accelerator, comprising a plurality of registers:
a memory; and
a configuration controller coupled to the hardware accelerator and to the memory, wherein the configuration controller, in operation, executes a finite state machine, wherein the finite state machine controls execution of a linked list of configuration operations, the linked list of configuration operations consisting of configuration operations selected from a defined set of configuration operations, wherein the executing the linked list of configuration operations configures the plurality of registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of a multi-stage processing task, wherein the configuration controller, in operation, retrieves a binary blob from the memory, the binary blob including the linked list of configuration operations.