US 12,411,693 B2
Apparatus for processor with hardware fence and associated methods
Mark W. Johnson, Austin, TX (US); Eric Deal, Austin, TX (US); and Junkang Ren, Austin, TX (US)
Assigned to Silicon Laboratories Inc., Austin, TX (US)
Filed by Silicon Laboratories Inc., Austin, TX (US)
Filed on Dec. 30, 2020, as Appl. No. 17/138,841.
Prior Publication US 2022/0206799 A1, Jun. 30, 2022
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3838 (2013.01) [G06F 9/3834 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a pipelined processor comprising branched parallel processing paths for instructions, and a hardware fence that maintains increasing transaction identifications (IDs) representing a submitted order on when instructions enter and are being processed within the branched parallel processing paths, wherein the increasing transaction IDs representing the submitted order are checked at a pipeline element level to stall a pipeline element when advancement of a pipeline stage of the branched parallel processing paths would produce an erroneous result.