US 12,411,689 B2
Method to reduce register access latency in split-die SoC designs
Anand K. Enamandram, Folsom, CA (US); Eswaramoorthi Nallusamy, Cedar Park, TX (US); Ramamurthy Krithivas, Chandler, AZ (US); Cheng-Wein Lin, Portland, OR (US); and Irene Johansen, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 16, 2021, as Appl. No. 17/552,843.
Prior Publication US 2022/0107808 A1, Apr. 7, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30101 (2013.01) [G06F 9/3863 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method implemented on a multi-socket platform comprising a plurality of sockets including a legacy socket and one or more non-legacy sockets, each of the legacy and non-legacy sockets comprising a split-die System-on-Chip (SoC) including a plurality of dielets interconnected with a plurality of embedded interconnect bridges connecting multiple dies, wherein the plurality of dielets include at least two core dielets having a plurality of cores, a plurality of cache controllers, and one or more memory controllers coupled to system memory, the method comprising:
accessing, on a non-legacy socket, control and status registers (CSRs) residing in the one or more memory controllers on the at least two core dielets using a plurality of transactions originating from a first core on a first core dielet of the at least two core dielets, wherein the plurality of transactions are forwarded via core-to-cache controller datapaths that do not cross an embedded interconnect bridges connecting multiple dies.