US 12,411,688 B2
Gather buffer management for unaligned and gather load operations
Kimberly M. Fernsler, Cedar Park, TX (US); Bryan Lloyd, Austin, TX (US); David A. Hrusecky, Cedar Park, TX (US); and David Campbell, Austin, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jul. 25, 2023, as Appl. No. 18/225,911.
Application 18/225,911 is a continuation of application No. 17/462,620, filed on Aug. 31, 2021, granted, now 11,755,324.
Prior Publication US 2023/0367595 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30043 (2013.01) [G06F 9/30036 (2013.01); G06F 9/3858 (2023.08)] 18 Claims
OG exemplary drawing
 
1. A computer system for executing instructions for loading and storing data, the computer system comprising:
a load launch queue receiving and storing a load data instruction issued from an instruction issuing unit;
a first logic circuit configured to examine a load address corresponding to the load data instruction issued from the instruction issuing unit and detect if the load address corresponds to an unaligned load data instruction;
a second logic circuit for processing the issued load data instruction, said processing of the issued load data instruction comprising: generating, in response to detecting the load address corresponds to an unaligned load data instruction, a first unaligned load signal and a second unaligned load signal to track a respective first partial unaligned load data result stored in a memory and second partial unaligned load data result stored in the memory;
a gather buffer comprising a plurality of storage entries storing a plurality of partial unaligned load data results retrieved from the memory;
a gather buffer controller circuit responsive to receiving said first unaligned load signal for retrieving and temporarily storing the first partial unaligned load data result in a storage entry of the gather buffer, said gather buffer controller circuit further responsive to receiving said second unaligned load signal for retrieving from the memory the second partial unaligned load data result for merging with the first partial unaligned load data result stored in the storage entry of said gather buffer at an arbitrary later time to satisfy said unaligned load data instruction; and
a circuit for merging the first partial unaligned load data result stored in the storage entry of said gather buffer with the second partial unaligned load data result retrieved from the memory, wherein said first logic circuit detects whether a load data stored in the memory at the load address is unaligned by examining the load address and a size of the load data stored in the memory at the load address and detecting whether the load data stored in the memory crosses a cache memory line storage boundary thereby requiring multiple memory accesses.