US 12,411,686 B2
Accelerated processing device and method of sharing data for machine learning
Maxim V. Kazakov, San Diego, CA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 30, 2021, as Appl. No. 17/364,780.
Prior Publication US 2023/0004385 A1, Jan. 5, 2023
Int. Cl. G06F 15/80 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06N 20/00 (2019.01)
CPC G06F 9/3001 (2013.01) [G06F 9/3012 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/5016 (2013.01); G06F 9/5072 (2013.01); G06F 9/544 (2013.01); G06F 15/8007 (2013.01); G06F 15/8046 (2013.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A processing device comprising:
a plurality of compute units configured to process data;
a plurality of arithmetic logic units that are each communicatively coupled to at least one of the plurality of compute units, each arithmetic logic unit including a memory configured to store a portion of the data, wherein the plurality of arithmetic logic units are configured to perform calculations using the data stored among the plurality of arithmetic logic units; and
an interconnect network, connecting the arithmetic logic units, configured to enable direct data access to the memory of each of the arithmetic logic units by any of the arithmetic logic units.