US 12,411,617 B1
Memory system including ECC engine
Seong Yoon Kang, Gyeonggi-do (KR); Mun Seon Jang, Gyeonggi-do (KR); and Sang Uhn Cha, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jun. 11, 2024, as Appl. No. 18/739,334.
Claims priority of application No. 10-2024-0031974 (KR), filed on Mar. 6, 2024.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0673 (2013.01)] 13 Claims
OG exemplary drawing
 
9. A memory system comprising:
a memory core; and
an ECC engine configured to, during a write operation, perform a logical operation on an M-bit write data to be stored in the memory core and an H matrix, and generate a 16-bit first error correction code and a 16-bit second error correction code, where M is an integer that is a multiple of 16,
wherein the H matrix comprises an upper matrix having a size of 16*(M+32) and a lower matrix having a size of 16*(M+32), and
wherein the lower matrix comprises a zero matrix having a size of 16*16, an identity matrix having a size of 16*16, and M/16 Tk companion matrices each having a size of 16*16, and k of the Tk companion matrices has values which are positive integers different by 16 or more for each companion matrix.