US 12,411,614 B2
Memory device for suppressing hot carrier injection and method of operating the same
Jong Wook Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 20, 2023, as Appl. No. 18/099,386.
Claims priority of application No. 10-2022-0089582 (KR), filed on Jul. 20, 2022.
Prior Publication US 2024/0028220 A1, Jan. 25, 2024
Int. Cl. G11C 16/26 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 13/1673 (2013.01); G11C 16/26 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory block including pages configured of a plurality of memory cells;
a peripheral circuit configured to perform a read operation on a selected page, among the pages; and
a control logic configured to control the peripheral circuit to perform a first read operation on a first logical page and then perform a second read operation on a second logical page, among the first and second logical pages in the selected page, during the read operation,
wherein the control logic is configured to:
control the peripheral circuit to adjust a channel initialization time according to the first logical page after the first read operation is ended,
perform a channel initialization operation during the channel initialization time during the second read operation,
adjust the channel initialization time according to a result of comparing a level of the first logical page with a level of the second logical page.