| CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] | 16 Claims |

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1. A non-volatile memory device comprising:
a memory cell array including a plurality of memory blocks each including a plurality of memory cells respectively connected to a plurality of word lines;
a block decoder configured to generate a first block selection signal and select a first block of the plurality of memory blocks based on the first block selection signal;
a plurality of first pass transistors each connected to one side of one of the plurality of word lines of the first block;
a plurality of second pass transistors each connected to the other side of one of the plurality of word lines of the first block;
a voltage generator configured to generate a plurality of operating voltages and to apply the plurality of operating voltages to the memory cell array;
in response to a first switch control signal, a first switch circuit configured to connect the plurality of first pass transistors to the voltage generator and to apply a corresponding first voltage of the plurality of operating voltages to the one side of one of the plurality of word lines of the first block through a corresponding one of the plurality of first pass transistors; and
in response to a second switch control signal different from the first switch control signal, a second switch circuit configured to connect the plurality of second pass transistors to the voltage generator and to apply the corresponding first voltage to the other side of one of the plurality of word lines of the first block through a corresponding one of the plurality of second pass transistors,
wherein the one side of one of the plurality of word lines of the first block is directly connected to the other side of one of the plurality of word lines of the first block, in the same word line,
wherein the first switch circuit and the one side of one of the plurality of word lines of the first block are connected to each other through the corresponding one of the plurality of first pass transistors in response to the first block selection signal, and
wherein the second switch circuit and the other side of one of the plurality of word lines of the first block are connected to each other through the corresponding one of the plurality of second pass transistors in response to the first block selection signal.
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