US 12,411,611 B2
Method and device for testing memory with instruction signal
Yu Li, Hefei (CN); and Beiyou Zhao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 28, 2022, as Appl. No. 17/954,556.
Application 17/954,556 is a continuation of application No. PCT/CN2022/098451, filed on Jun. 13, 2022.
Claims priority of application No. 202210519509.1 (CN), filed on May 12, 2022.
Prior Publication US 2023/0014477 A1, Jan. 19, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for testing a memory, comprising:
sending an instruction signal to the memory, the instruction signal comprising a write instruction or a read instruction;
randomly inserting a valid Column Address Strobe (CAS) instruction before the instruction signal by detecting a specific type of the instruction signal, the CAS instruction being used to ensure that the instruction signal is run, and randomly generating and inserting at least one of a redundant CAS instruction or invalid command irrelevant to the instruction signal;
running the instruction signal, the inserted valid CAS instruction, and the at least one of the redundant CAS instruction or the invalid command by the memory; and
testing the running of the instruction signal by the memory;
wherein randomly inserting the valid CAS instruction for ensuring the running of the instruction signal before the instruction signal, and randomly generating and inserting the at least one of the redundant CAS instruction or invalid command irrelevant to the instruction signal comprises:
detecting a type of a previous valid CAS instruction and determining whether an execution of a current instruction signal is ensured;
responsive to that the execution of the current instruction signal is ensured, detecting a time interval between the current instruction signal and the previous valid CAS instruction;
determining whether a sum of the time interval and a time of the invalid command to be inserted is longer than a maintenance duration of the previous valid CAS instruction, wherein in the maintenance duration, the write instruction or the read instruction is executed; and
responsive to that the sum of time is longer than the maintenance duration, determining whether the time interval is longer than the maintenance duration, and responsive to that the time interval is longer than the maintenance duration, inserting the valid CAS instruction for ensuring the running of the instruction signal before the current instruction signal, and randomly inserting the at least one of the redundant CAS instruction or the invalid command between the inserted valid CAS instruction and the current instruction signal.