| CPC G06F 3/0613 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0673 (2013.01)] | 14 Claims |

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1. A continuous memory access acceleration circuit for signal processing of a biquad filter, comprising:
a register circuit;
an arithmetic circuit coupled to the register circuit and calculating a memory access address according to temporary data provided by the register circuit; and
an address shift circuit coupled to the register circuit and the arithmetic circuit, wherein the address shift circuit comprises:
a counter providing a count value;
a counting control circuit coupled to the register circuit and the counter and controlling the counter to accumulate the count value according to a number of times a memory is accessed, wherein the counting control circuit controls the counter to accumulate the count value in response to the number of times memory are accessed reaching a preset number of times, the preset number of times is 2; and
an adder circuit coupled to the arithmetic circuit and the counter and adding the memory access address and the count value to generate a target memory access address.
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