US 12,411,606 B2
High capacity memory circuit with low effective latency
Youn Cheul Kim, Saratoga, CA (US); Richard S. Chernicoff, Mercer Island, WA (US); Khandker Nazrul Quader, Santa Clara, CA (US); Robert D. Norman, Pendleton, OR (US); Tianhong Yan, Saratoga, CA (US); Sayeef Salahuddin, Walnut Creek, CA (US); and Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Jun. 21, 2024, as Appl. No. 18/750,979.
Application 18/750,979 is a continuation of application No. 18/306,073, filed on Apr. 24, 2023, granted, now 12,073,082.
Application 18/306,073 is a continuation of application No. 17/169,387, filed on Feb. 5, 2021, granted, now 11,675,500, issued on Jun. 1, 2023.
Claims priority of provisional application 62/971,720, filed on Feb. 7, 2020.
Prior Publication US 2024/0345736 A1, Oct. 17, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G06F 3/06 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0631 (2013.01); H01L 24/20 (2013.01); H01L 25/18 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1435 (2013.01)] 73 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first semiconductor die having memory circuits configured into a plurality of first memory modules formed above a substrate layer in the first semiconductor die, each first memory module comprising a plurality of memory cells organized into one or more arrays of memory strings, with the memory strings of each array being provided along first dimension and a second dimension, such that each memory string in the array extends along a third dimension, the first dimension, the second dimension and the third dimension being each mutually orthogonal to both the other two dimensions; and
a second semiconductor die having memory circuits configured into a plurality of second memory modules, wherein each second memory module is configurable to be associated with a group of one or more first memory modules, such that the memory circuits within each second memory module and memory circuits of its associated first memory modules are interconnected by interconnections formed by wafer-level or chip-level bonding between the first and second semiconductor dies.