US 12,411,603 B2
Memory device and operating method thereof
Jae Young Lee, Icheon-si (KR); and Han Bin Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 16, 2023, as Appl. No. 18/451,020.
Claims priority of application No. 10-2023-0026926 (KR), filed on Feb. 28, 2023.
Prior Publication US 2024/0289014 A1, Aug. 29, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0608 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells;
a data manager configured to receive data from the plurality of memory cells and generate sub-data groups, each sub-data group being a predetermined number of bits, the number of bits comprising a sub-data group being determined from the number of bits comprising the received data; and
a data compressor configured to detect first-value bits in the received data, the data compressor being additionally configured to determine a number of target bits in each of the sub-data groups among the first-value bits and generate a plurality of compressed-data chunks, each compressed-data chunk including the target bits and position information representing a position of the target bits in the received data.