US 12,411,538 B2
System-wide low power management
Benjamin Tsien, Santa Clara, CA (US); Greggory D. Donley, Santa Clara, CA (US); and Bryan P. Broussard, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jul. 2, 2021, as Appl. No. 17/366,423.
Application 17/366,423 is a continuation of application No. 15/856,546, filed on Dec. 28, 2017, granted, now 11,054,887, issued on Jul. 6, 2021.
Prior Publication US 2021/0333860 A1, Oct. 28, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/32 (2019.01); G06F 1/3209 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01); G06F 9/50 (2006.01)
CPC G06F 1/3287 (2013.01) [G06F 1/3209 (2013.01); G06F 1/3234 (2013.01); G06F 1/3296 (2013.01); G06F 9/5094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A first processing node comprising:
at least one link coupled to a second processing node;
one or more clients comprising circuitry configured to process tasks; and
a power controller comprising circuitry;
wherein responsive to receipt of an indication from the second processing node that each client in the second processing node is idle and each client in a third processing node is idle:
the power controller is configured to power down the at least one link and the one or more clients, responsive to all of the one or more clients in the first processing node being idle;
the first processing node is configured to convey a non-idle indication to the second processing node, responsive to fewer than all of the one or more clients of the first processing node being idle.