US 12,411,537 B2
Power reduction for systems having multiple ranks of memory
Hyunjoon Kang, Suwon-si (KR); and Taehun Kim, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 24, 2023, as Appl. No. 18/159,022.
Claims priority of application No. 10-2022-0011791 (KR), filed on Jan. 26, 2022; and application No. 10-2022-0085278 (KR), filed on Jul. 11, 2022.
Prior Publication US 2023/0236653 A1, Jul. 27, 2023
Int. Cl. G06F 1/3234 (2019.01); G06F 3/06 (2006.01); G11C 5/14 (2006.01); G11C 11/406 (2006.01)
CPC G06F 1/3275 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/067 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a memory system including first and second memory ranks; and
a memory controller connected to the memory system and configured to control power of the memory system,
the memory controller further configured to cause the first memory rank to enter an idle power down (IPD) state during memory access in which a data toggle time without a data bubble is equal to or greater than an IPD minimum gain duration in another bank access for the second memory rank; and
wherein the IPD minimum gain duration includes a rank-to-rank switching time, a per-bank refresh cycle time and a delay time from issuance of an active command to application of a write/read command.