US 12,411,518 B2
Throttle control circuits for throttling activity in processing segment circuits in an integrated circuit (IC) chip and related methods
Sagar Koorapati, Austin, TX (US); and Alon Naveh, Corte Madera, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jun. 22, 2023, as Appl. No. 18/339,478.
Prior Publication US 2024/0427368 A1, Dec. 26, 2024
Int. Cl. G06F 1/08 (2006.01); G06F 1/3228 (2019.01); G06F 1/324 (2019.01)
CPC G06F 1/08 (2013.01) [G06F 1/3228 (2013.01); G06F 1/324 (2013.01)] 28 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip comprising a processor-based system, the processor-based system comprising:
a first plurality of processing segment circuits, each configured to operate in response to a clock signal; and
a throttle control circuit comprising:
a plurality of throttle administration circuits, each configured to receive a throttle control signal and generate a throttle select signal, based on the throttle control signal, to a corresponding one of the first plurality of processing segment circuits; and
a throttle sequence selection circuit configured to provide, to each of the first plurality of processing segment circuits, an activity control signal configured to throttle activity in the processing segment circuit in a first number (M) of cycles among a second number (N) of consecutive cycles of the clock signal based on a corresponding throttle select signal.