US 12,411,512 B2
Low dropout regulator, clock generating circuit, and memory device
Takahiro Nomiyama, Suwon-si (KR); and Yongmin Kim, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 19, 2023, as Appl. No. 18/490,240.
Claims priority of application No. 10-2022-0137764 (KR), filed on Oct. 24, 2022; and application No. 10-2022-0186388 (KR), filed on Dec. 27, 2022.
Prior Publication US 2024/0184320 A1, Jun. 6, 2024
Int. Cl. G05F 1/575 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01)
CPC G05F 1/575 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A low dropout (LDO) regulator configured to generate first to nth output voltages, where n is a natural number greater than or equal to 2, and each of the first to nth output voltages corresponds to a reference voltage, the LDO regulator comprising:
an amplifier configured to generate an error voltage based on the reference voltage and a first output voltage of the first to nth output voltages;
a trimming control circuit configured to generate first to (n−1)th trimming signals based on the first to nth output voltages; and
an output buffer circuit configured to generate the first to nth output voltages based on the error voltage and the first to (n−1)th trimming signals.