US 12,411,175 B2
Integrated circuit package for scan testing semiconductor chip, operating method of integrated circuit package, and integrated circuit
Taewoong Ahn, Suwon-si (KR); Youngin Park, Suwon-si (KR); and Junyeong Jang, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 15, 2023, as Appl. No. 18/450,043.
Claims priority of application No. 10-2022-0102950 (KR), filed on Aug. 17, 2022.
Prior Publication US 2024/0061040 A1, Feb. 22, 2024
Int. Cl. G01R 31/3185 (2006.01)
CPC G01R 31/318536 (2013.01) [G01R 31/318547 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit package for scan testing a semiconductor chip, the integrated circuit package comprising:
at least one first input pad configured to receive a first input signal;
at least one chip connected to the at least one first input pad; and
at least one first output pad configured to receive a first output signal generated from the at least one chip, wherein
each of the at least one chip comprises
at least one second input pad configured to receive a second input signal;
a plurality of scan chains;
a first test circuit and a second test circuit sharing the plurality of scan chains; and
at least one second output pad configured to receive a second output signal from the first test circuit, wherein
the integrated circuit package comprises
a signal selection circuit configured to receive a selection signal and determine whether the first input signal is used in the first test circuit or the second test circuit, based on the selection signal.