US 12,082,513 B2
Memory cells with asymmetrical electrode interfaces
Agostino Pirovano, Milan (IT); Kolya Yastrebenetsky, Boise, ID (US); Anna Maria Conti, Milan (IT); and Fabio Pellizzer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 21, 2021, as Appl. No. 17/480,694.
Application 17/480,694 is a division of application No. 16/856,631, filed on Apr. 23, 2020, granted, now 11,133,463.
Application 16/706,358 is a division of application No. 15/893,108, filed on Feb. 9, 2018, granted, now 10,541,364, issued on Jan. 21, 2020.
Application 16/856,631 is a continuation of application No. 16/706,358, filed on Dec. 6, 2019, granted, now 10,672,981, issued on Jun. 2, 2020.
Prior Publication US 2022/0059763 A1, Feb. 24, 2022
Int. Cl. H10N 70/00 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/8416 (2023.02) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H10B 63/80 (2023.02); H10N 70/011 (2023.02); H10N 70/063 (2023.02); H10N 70/231 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/8418 (2023.02); H10N 70/882 (2023.02); H10N 70/8822 (2023.02); H10N 70/8825 (2023.02); H10N 70/8828 (2023.02); G11C 2013/0045 (2013.01); G11C 2013/005 (2013.01); G11C 2013/0078 (2013.01); G11C 2013/009 (2013.01); G11C 2013/0092 (2013.01); G11C 2213/13 (2013.01); G11C 2213/52 (2013.01); G11C 2213/73 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a self-selecting memory component;
a top electrode in physical contact with a digit line and comprising a first interface with the self-selecting memory component having a first contact area; and
a bottom electrode in physical contact with a word line and comprising a second interface with the self-selecting memory component having a second contact area that is less than the first contact area of the first interface.