US 12,082,465 B2
Display device with reduced parasitic capacitances between pixel electrodes and data lines
Jun Hyun Park, Suwon-si (KR); Dong Woo Kim, Yongin-si (KR); Sung Jae Moon, Seongnam-si (KR); and Kang Moon Jo, Hwaseong-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Jun. 22, 2023, as Appl. No. 18/212,733.
Application 18/212,733 is a continuation of application No. 16/869,673, filed on May 8, 2020, granted, now 11,723,241.
Claims priority of application No. 10-2019-0065232 (KR), filed on Jun. 3, 2019.
Prior Publication US 2023/0337488 A1, Oct. 19, 2023
Int. Cl. H10K 59/131 (2023.01); H01L 49/02 (2006.01); H10K 59/121 (2023.01); H10K 59/123 (2023.01); H10K 59/35 (2023.01)
CPC H10K 59/131 (2023.02) [H01L 28/60 (2013.01); H10K 59/1216 (2023.02); H10K 59/123 (2023.02); H10K 59/35 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A display device comprising:
a first pixel circuit portion including at least one transistor;
a second pixel circuit portion including at least one transistor;
a first pixel electrode electrically connected to the first pixel circuit portion;
a second pixel electrode electrically connected to the second pixel circuit portion;
a first data line electrically connected to the first pixel circuit portion; and
a second data line electrically connected to the second pixel circuit portion,
wherein the first data line and the second data line are arranged along a first direction,
wherein the first pixel circuit portion and the second pixel circuit portion are arranged along a second direction perpendicular to the first direction,
wherein the first pixel electrode does not overlap the first data line and the second data line in a plan view, and
wherein the second pixel electrode overlaps the first data line and the second data line in the plan view.