US 12,082,455 B2
Display device
Fumiyuki Kobayashi, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Appl. No. 18/266,275
Filed by SHARP KABUSHIKI KAISHA, Sakai (JP)
PCT Filed Dec. 11, 2020, PCT No. PCT/JP2020/046314
§ 371(c)(1), (2) Date Jun. 9, 2023,
PCT Pub. No. WO2022/123776, PCT Pub. Date Jun. 16, 2022.
Prior Publication US 2024/0049527 A1, Feb. 8, 2024
Int. Cl. H10K 59/126 (2023.01); G09G 3/3233 (2016.01); H10K 59/131 (2023.01)
CPC H10K 59/126 (2023.02) [G09G 3/3233 (2013.01); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A display device comprising: a light-emitting element; a first data signal line to which a signal corresponding to video data is supplied in a vertical scanning period and a signal not corresponding to video data is supplied in an update pause period; a drive transistor configured to control a current value of the light-emitting element; a conductor electrically connected to a gate electrode of the drive transistor; a shield electrode located between the first data signal line and the conductor and adjacent to each of the first data signal line and the conductor in a plan view, a silicon film; a first metal layer at an upper layer compared to the silicon film; a second metal layer at an upper layer compared to the first metal layer; an oxide semiconductor film at an upper layer compared to the second metal layer; a third metal layer at an upper layer compared to the oxide semiconductor film; and a fourth metal layer at an upper layer compared to the third metal layer a fourth metal layer at an upper layer compared to the third metal layer;
a transistor; and
a set transistor having an electrode directly connected to the gate electrode of the drive transistor, and each of the transistor and the set transistor having a gate electrode directly connected to a corresponding scanning signal line,
wherein the gate electrode of the drive transistor is connected to a drain electrode of the drive transistor via the set transistor and is connected to an initialization signal line via the transistor, and the shield electrode and the silicon film do not overlap each other in a plan view.