US 12,082,421 B2
Semiconductor device and method for manufacturing the same
Tzu-Yu Chen, Hsinchu (TW); Sheng-Hung Shih, Hsinchu (TW); Fu-Chen Chang, Hsinchu (TW); Kuo-Chi Tu, Hsinchu (TW); and Wen-Ting Chu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 26, 2023, as Appl. No. 18/324,245.
Application 18/324,245 is a continuation of application No. 17/331,926, filed on May 27, 2021, granted, now 11,706,930.
Prior Publication US 2023/0309318 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 49/02 (2006.01); H10B 53/30 (2023.01)
CPC H10B 53/30 (2023.02) [H01L 21/0234 (2013.01); H01L 21/02356 (2013.01); H01L 28/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a ferroelectric memory cell, comprising:
forming a bottom electrode;
forming a ferroelectric layer on the bottom electrode;
forming a top electrode layer on the ferroelectric layer opposite to the bottom electrode;
patterning the top electrode layer to form a top electrode such that the ferroelectric layer has a first portion covered by the top electrode and a second portion exposed from the top electrode;
performing a first plasma treatment to the second portion of the ferroelectric layer; and
after the first plasma treatment, patterning the second portion of the ferroelectric layer to form a data storage element which includes the first portion and the patterned second portion of the ferroelectric layer, the patterned second portion of the ferroelectric layer having at least 60% of ferroelectric phase, the bottom electrode, the data storage element and the top electrode together forming the ferroelectric memory cell.