CPC H10B 51/20 (2023.02) [G11C 7/18 (2013.01); H10B 51/10 (2023.02)] | 9 Claims |
1. A method for forming a semiconductor structure, comprising:
providing a substrate, wherein a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate;
etching the active layer and the sacrificial layer to form active lines along a first direction;
forming a first isolation layer that fills spacing between the active lines;
etching end portions of the active lines to form openings exposing the sacrificial layer;
removing the sacrificial layer along the openings, and forming gaps between a bottom of the active lines and the substrate;
filling the gaps with a conductive material to form bit lines extending along the first direction;
patterning the active lines to form a plurality of active columns that are discrete, the plurality of active columns being arranged in an array along the first direction and a second direction; and
forming a first doped region, a channel region, and a second doped region that are located on a bottom of an active column and sequentially arranged upwards, and forming a gate structure surrounding the channel region;
wherein a method for forming the first doped region comprises: forming a transitional layer with doping elements on the substrate between adjacent active lines or active columns, after the active lines or active columns are formed; and through diffusion treatment, diffusing at least part of the doping elements in the transitional layer into the active line or the active column to form the first doped region.
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