US 12,082,418 B2
Semiconductor memory device
Keisuke Uchida, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jul. 29, 2022, as Appl. No. 17/877,056.
Application 17/877,056 is a continuation of application No. 16/505,851, filed on Jul. 9, 2019, granted, now 11,437,394.
Claims priority of application No. 2019-037445 (JP), filed on Mar. 1, 2019.
Prior Publication US 2022/0367507 A1, Nov. 17, 2022
Int. Cl. H01L 27/11573 (2017.01); H01L 27/11582 (2017.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/40 (2023.02) [H10B 43/27 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a lower layer structure including a peripheral circuit provided on a substrate, the substrate including a first region and a second region arranged in a first direction, the first region including first and second sub-regions and an intermediate region arranged between the first and second sub-regions in the first direction;
a stacked structure which is provided above the lower layer structure and in which a plurality of first insulating layers and a plurality of conducting layers are alternately stacked in a second direction perpendicular to the first direction within the first and second sub-regions, and the plurality of first insulating layers and a plurality of second insulating layers different in material from the first insulating layers are alternately stacked in the second direction within the intermediate region and the second region; and
a first pillar which includes a first memory layer and a first channel layer adjacently arranged sequentially from an outer surface of the first pillar, extends in the second direction through the stacked structure within one of the first and second sub-regions, and has an end reaching a layer of a semiconductor doped with impurities, and in which a bottom surface of the first channel layer is connected with the layer of the semiconductor, and first memory cells are formed at intersections with at least some of the plurality of conducting layers within the one of the first and second sub-regions, wherein
the plurality of first insulating layers in the stacked structure is provided across the first region and the second region in the first direction so as not to be isolated within the intermediate region,
the plurality of conducting layers and the plurality of second insulating layers in the stacked structure are coupled with each other in the first direction, and
the plurality of second insulating layers within the second region is provided in the first direction from a coupling portion with the plurality of conducting layers within the one of the first and second sub-regions to a device end surface corresponding to a cut position of the substrate that forms a chip.