CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] | 20 Claims |
1. A semiconductor device comprising:
a substrate;
a lower stack structure on the substrate, and including lower gate electrodes stacked apart from each other;
an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other;
a lower channel structure penetrating through the lower stack structure, and including a lower channel layer and a lower channel insulating layer on the lower channel layer, the lower channel insulating layer surrounding a lower slit; and
an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit,
wherein the lower channel structure includes a first channel structure, a second channel structure on the first channel structure, and a bent structure between the first channel structure and the second channel structure, a bend in the bent structure corresponding to a difference in widths between the first and second channel structures,
a width of a lower portion of the upper channel structure is less than a width of an upper portion of the lower channel structure, and
a maximum width of the lower slit is greater than a maximum width of the upper slit.
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