CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 14 Claims |
1. A three-dimensional (3D) memory device, comprising:
a core region, comprising:
a first drain-select-gate (DSG) cut structure extending along a first direction and a vertical direction; and
a dummy channel structure located under the first DSG cut structure and extending along the vertical direction; and
a staircase region comprising a plurality of stairs each comprising at least a conductor/dielectric pair extending in the first direction, the staircase region comprising:
a second drain-select-gate (DSG) cut structure extending along the first direction and the vertical direction, and
a plurality of support structures extending in the second DSG cut structure along the vertical direction, wherein of at least one of the support structures, a dimension along the first direction is greater than a dimension along a second direction perpendicular to the first direction,
wherein the first DSG cut structure in the core region is aligned with the second DSG cut structure in the staircase region along the first direction.
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