US 12,082,413 B2
Vertical semiconductor memory device having stacked shifted axis channels
Toshiyuki Sasaki, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Apr. 21, 2021, as Appl. No. 17/236,517.
Application 17/236,517 is a continuation of application No. 16/872,485, filed on May 12, 2020.
Application 16/872,485 is a continuation of application No. 16/439,766, filed on Jun. 13, 2019, granted, now 10,682,779, issued on Jun. 16, 2020.
Application 16/439,766 is a continuation of application No. 15/818,793, filed on Nov. 21, 2017, granted, now 10,369,715, issued on Aug. 6, 2019.
Application 15/818,793 is a continuation of application No. 15/427,676, filed on Feb. 8, 2017, granted, now 9,865,618, issued on Jan. 9, 2018.
Application 15/427,676 is a continuation of application No. 15/213,537, filed on Jul. 19, 2016, granted, now 9,608,002, issued on Mar. 28, 2017.
Application 15/213,537 is a continuation of application No. 14/958,995, filed on Dec. 4, 2015, granted, now 9,425,211, issued on Aug. 23, 2016.
Application 14/958,995 is a continuation of application No. 14/464,223, filed on Aug. 20, 2014, granted, now 9,236,395, issued on Jan. 12, 2016.
Claims priority of provisional application 62/016,908, filed on Jun. 25, 2014.
Prior Publication US 2021/0237293 A1, Aug. 5, 2021
Int. Cl. H10B 43/27 (2023.01); G11C 16/10 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/10 (2006.01); H01L 29/792 (2006.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01); A45F 5/02 (2006.01); B24B 3/54 (2006.01); B26B 29/02 (2006.01)
CPC H10B 43/27 (2023.02) [G11C 16/10 (2013.01); H01L 21/31116 (2013.01); H01L 23/528 (2013.01); H01L 23/53257 (2013.01); H01L 23/53261 (2013.01); H01L 29/1037 (2013.01); H01L 29/7926 (2013.01); H10B 43/20 (2023.02); H10B 43/35 (2023.02); A45F 5/021 (2013.01); B24B 3/54 (2013.01); B26B 29/025 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a source layer;
a first unit provided above the source layer, the first unit including at least a source-side selection gate layer;
a second unit stacked above the first unit, the second unit including a plurality of first electrode layers as control gates of memory cells, the first electrode layers being alternately stacked in a stacking direction with a plurality of first insulating layers therebetween;
a bit line provided above the second unit;
a first columnar part piercing the first unit in the stacking direction, the first columnar part including a first channel body with a tubular configuration and a first core insulator part provided inside the first channel body with the tubular configuration; and
a second columnar part piercing the second unit in the stacking direction, the second columnar part including a second channel body with a tubular configuration and a second core insulator part provided inside the second channel body with the tubular configuration, wherein
the first channel body and the second channel body are formed as one body and are connected with each other in the stacking direction, and
a central axis of the first columnar part piercing the first unit is shifted in a direction perpendicular to the stacking direction from a central axis of the second columnar part piercing the second unit.