US 12,082,411 B2
Three-dimensional memory device with backside interconnect structures
Kun Zhang, Wuhan (CN); Zhong Zhang, Wuhan (CN); Lei Liu, Wuhan (CN); Wenxi Zhou, Wuhan (CN); and Zhiliang Xia, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Sep. 14, 2020, as Appl. No. 17/020,383.
Application 17/020,383 is a continuation of application No. PCT/CN2020/100567, filed on Jul. 7, 2020.
Prior Publication US 2021/0320122 A1, Oct. 14, 2021
Int. Cl. H10B 43/27 (2023.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers on a first side of a semiconductor layer;
a plurality of channel structures each extending vertically through the memory stack and in contact with the first side of the semiconductor layer;
a plurality of source contacts in contact with a second side of the semiconductor layer opposite to the first side;
a plurality of contacts through the semiconductor layer; and
a backside interconnect layer on the second side of the semiconductor layer and comprising a source line mesh in a plan view, wherein the plurality of source contacts and a first set of the plurality of contacts are in contact with the source line mesh.