| CPC H10B 43/10 (2023.02) [H10B 12/00 (2023.02); H10B 12/03 (2023.02); H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10B 12/31 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] | 19 Claims |
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1. A semiconductor device comprising:
a substrate;
a first insulation pattern on the substrate;
a second insulation pattern on the first insulation pattern;
a third insulation pattern between the first insulation pattern and the second insulation pattern, the third insulation pattern having a recess that exposes a top surface of the first insulation pattern, a bottom surface of the second insulation pattern, and a side surface of the third insulation pattern;
a semiconductor pattern arranged in the recess of the third insulation pattern and extending in a first direction that is parallel to a top surface of the substrate, the semiconductor pattern including a first end, a second end facing the first end, and a channel region between the first end and second end;
a bit line arranged between the first insulation pattern and the second insulation pattern, and contacting the first end of the semiconductor pattern, the bit line extending in a second direction that is parallel to the top surface of the substrate and that is perpendicular to the first direction;
a word line arranged adjacent to the channel region of the semiconductor pattern, and extending in a third direction that is perpendicular to the top surface of the substrate;
a gate dielectric layer between the semiconductor pattern and the word line; and
a capacitor lower electrode contacting the second end of the semiconductor pattern, and extending in the first direction,
wherein the channel region is a portion of the semiconductor pattern that neighbors the word line in the second direction,
wherein a first side surface of the channel region of the semiconductor pattern contacts the side surface of the third insulation pattern,
a second side surface of the channel region of the semiconductor pattern contacts the gate dielectric layer,
a top surface of the channel region of the semiconductor pattern contacts the bottom surface of the second insulation pattern, and
a bottom surface of the channel region of the semiconductor pattern contacts the top surface of the first insulation pattern.
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