| CPC H10B 41/35 (2023.02) [H01L 27/0802 (2013.01); H10B 41/10 (2023.02); H10B 41/41 (2023.02)] | 20 Claims |
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1. An active resistor array of a semiconductor memory device, comprising:
a first active resistor in a first active resistor region;
a second active resistor in the first active resistor region and arranged in parallel with the first active resistor, and an isolation element layer interposed between the second active resistor and the first active resistor;
a third active resistor in a second active resistor region;
a first selection transistor in a first selection transistor region and connected to the second active resistor; and
a second selection transistor in a second selection transistor region and connected to the third active resistor;
wherein the first and second selection transistors are connected to a same gate layer, and
the gate layer of the first and second selection transistors is on the isolation element layer.
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