US 12,082,403 B1
One time programmable bitcell with select device in isolated well
Andrew Edward Horch, Seattle, WA (US); Oleg Ivanov, Ottawa (CA); and Larry Wang, San Jose, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Jun. 24, 2022, as Appl. No. 17/849,413.
Claims priority of provisional application 63/214,726, filed on Jun. 24, 2021.
Int. Cl. G11C 17/16 (2006.01); G11C 17/18 (2006.01); H01L 23/525 (2006.01); H10B 20/20 (2023.01)
CPC H10B 20/20 (2023.02) [G11C 17/16 (2013.01); G11C 17/18 (2013.01); H01L 23/5252 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory comprising:
M×N select transistors disposed along M rows and N columns, wherein M and N are integers greater than or equal to 2;
a first set of M wells each configured to be biased independently of a remaining M−1 wells and each having formed therein the N of the select transistors, wherein the N select transistors disposed in each well have a source/drain terminal coupled to a same bitline corresponding to a different one of M bitlines of the memory; and
M×N anti-fuses, each anti-fuse being associated and forming a bitcell with a corresponding one of the M×N select transistors.