CPC H10B 12/37 (2023.02) [G11C 5/10 (2013.01); G11C 11/221 (2013.01); G11C 11/4023 (2013.01); H10B 53/20 (2023.02)] | 19 Claims |
1. A memory device, comprising:
an array of memory cells, each comprising a vertical transistor, and a storage unit coupled to the vertical transistor, wherein the array of memory cells is arranged in rows in a first direction and columns in a second direction, two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view;
a plurality of word lines each extending in the second direction; and
a plurality of slit structures each extending in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction,
wherein:
the array of memory cells further comprises a first set of function memory cells each coupled to a first word line of the plurality of word lines, a second set of function memory cells each coupled to a second word line of the plurality of word lines adjacent to the first word line, and a set of dummy memory cells each coupled to one of the plurality of slit structures having a straight shape in the plan view and separating the first word line and the second word line.
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