US 12,082,399 B2
Memory devices having vertical transistors in staggered layouts
Dongxue Zhao, Wuhan (CN); Tao Yang, Wuhan (CN); Yuancheng Yang, Wuhan (CN); Zhiliang Xia, Wuhan (CN); and Zongliang Huo, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 1, 2021, as Appl. No. 17/539,760.
Application 17/539,760 is a continuation of application No. PCT/CN2021/127797, filed on Oct. 31, 2021.
Prior Publication US 2023/0133520 A1, May 4, 2023
Int. Cl. H10B 12/00 (2023.01); G11C 5/10 (2006.01); G11C 11/22 (2006.01); G11C 11/402 (2006.01); H10B 53/20 (2023.01)
CPC H10B 12/37 (2023.02) [G11C 5/10 (2013.01); G11C 11/221 (2013.01); G11C 11/4023 (2013.01); H10B 53/20 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an array of memory cells, each comprising a vertical transistor, and a storage unit coupled to the vertical transistor, wherein the array of memory cells is arranged in rows in a first direction and columns in a second direction, two adjacent rows of the memory cells are staggered with one another, and two adjacent columns of the memory cells are staggered with one another in a plan view;
a plurality of word lines each extending in the second direction; and
a plurality of slit structures each extending in the second direction and separating two adjacent word lines of the plurality of word lines in the first direction,
wherein:
the array of memory cells further comprises a first set of function memory cells each coupled to a first word line of the plurality of word lines, a second set of function memory cells each coupled to a second word line of the plurality of word lines adjacent to the first word line, and a set of dummy memory cells each coupled to one of the plurality of slit structures having a straight shape in the plan view and separating the first word line and the second word line.