US 12,082,350 B2
Semiconductor device
Shingo Inoue, Yokohama (JP)
Assigned to SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC., Kanagawa (JP)
Filed by SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC., Kanagawa (JP)
Filed on Jul. 8, 2020, as Appl. No. 16/923,765.
Application 16/923,765 is a continuation of application No. 16/343,622, granted, now 10,750,621, previously published as PCT/JP2018/028924, filed on Aug. 1, 2018.
Claims priority of application No. 2017-150035 (JP), filed on Aug. 2, 2017.
Prior Publication US 2020/0404794 A1, Dec. 24, 2020
Int. Cl. H05K 3/34 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H05K 3/3421 (2013.01) [H01L 24/27 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H01L 2224/2732 (2013.01); H01L 2224/83855 (2013.01); H01L 2924/17788 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a metal base;
a semiconductor chip provided on the metal base, the semiconductor chip outputting an amplified output signal from an input signal;
a frame work located on the metal base, the frame work having a metal pattern including an input pattern configured to connect with an input of the semiconductor chip to provide the input signal to the input of the semiconductor chip, an output pattern configured to connect with an output of the semiconductor chip to output the amplified output signal from the semiconductor chip, and a bias pad configured to supply a bias voltage to the input of the semiconductor chip; and
an elongated metal pattern electrically connected between the bias pad and the input pattern, wherein
the bias pad and the elongated metal pattern supply a gate bias voltage to the input pattern of the semiconductor chip, and
the elongated metal pattern has a characteristic of isolation at a frequency around the input signal so as to isolate the bias pad from the input pattern at frequencies around the input signal.